USB Core


The USB Function Controller is a flexible solution to add USB functionality to virtually any application. It includes all functionality required to implement a USB bus interface within a single FPGA or ASIC device with only an external USB Transceiver required. Up to four Endpoints are supported, each of them easily attachable to standard micro controller busses.



  • fully Compliant to USB 1.1 specification
    • Full-Speed (12Mbps) operation
    • support for 4 endpoints, including up to 3 user-configurable Endpoints
    • supports Bulk, Interrupt, or Isochronous data transfers
  • hardwired USB protocol layer
    • no firmware intervention required
    • up to 10Mbps net bandwidth
  • very compact design
    • on-chip digital PLL
    • on-chip Endpoint-FIFOs
    • minimum gate count
    • optimized for FPGA implementation
  • lowest possible design risk
    • free behavioral model
    • comprehensive reference application
    • USB Packet-oriented test bench
    • synthesizable VHDL model
  • very low cost


The core was successfully synthesized with the following tools: Synopsys FPGA Express, Xilinx XST, Mentor Leonardo Spectrum. Resource usage depends on the endpoint configuration and size of the endpoint FIFOs. This is a summary of the required resources for a minimal HID design:

  • 4 input LUTs: 337
  • 3 input LUTs: 52
  • CLB Flip Flops: 203
  • 16×1 RAMs: 8
  • gate count: about 4k


The USB core was verified on different levels:

  • sub-module verification of critical entities, e.g. clock PLL
  • simulation of critical USB packet sequences
  • simulation of full USB device enumeration
  • real-life debugging with USB protocol analyzer
  • real-life test with reference applications

The following reference designs have been implemented:

  • HID reference design
  • flash programming application for FPGA development board
  • USB to CompactFlash adapter